#include "os_common.h"


//---------------------------------------------------------------------------------------------------
VOID hal_start_tx0( IN phw_data_t pHwData )
{
	if( !pHwData->SurpriseRemove ) Wb35Tx_start( pHwData );
}
//---------------------------------------------------------------------------------------------------
VOID hal_remove_mapping_key( phw_data_t pHwData, PUCHAR pmac_addr )
{
	ULONG	i;

	if( pHwData->SurpriseRemove ) return;

	#ifdef _PE_STATE_DUMP_
	WBDEBUG(("hal_remove_mapping_key\n"));
	#endif

	for( i=MAPPING_KEY_START_INDEX; i<MAX_KEY_TABLE; i++ )
	{
		if( OS_MEMORY_COMPARE( pmac_addr, pHwData->Key_slot[i], MAC_ADDR_LENGTH ) )
			break;
	}
	if( i != MAX_KEY_TABLE ) //Find the same index
	{
		// Clear the mac address
		OS_MEMORY_CLEAR( pHwData->Key_slot[i], MAC_ADDR_LENGTH );

		//Writing into register to clear the valid bit
		Wb35Reg_Write( pHwData, 0x0820, 0x0 );//Value
		i<<=4;
		i |= 0x4000000;
		Wb35Reg_Write( pHwData, 0x081c, i );
	}
}
//---------------------------------------------------------------------------------------------------
VOID hal_remove_default_key( phw_data_t pHwData, ULONG i )
{
	ULONG	ltmp;
	if( pHwData->SurpriseRemove ) return;

	#ifdef _PE_STATE_DUMP_
	WBDEBUG(("hal_remove_default_key\n"));
	#endif

	if( i < 4 ) // For default key index 0 ~ 3
	{
		//Writing into register to clear the valid bit
		Wb35Reg_Write( pHwData, 0x0820, 0x0 );//Value
		ltmp = i<<4;
		ltmp |= 0x4000000;
		Wb35Reg_Write( pHwData, 0x081c, ltmp );

		OS_MEMORY_CLEAR( pHwData->Key_slot[i], MAC_ADDR_LENGTH ); // 20060214 for recover
	}
}
//---------------------------------------------------------------------------------------------------
BOOLEAN hal_set_mapping_key( phw_data_t pHwData, IN PUCHAR pmac_addr, IN UCHAR null_key,
							 IN UCHAR wep_on, IN PUCHAR ptx_tsc, IN PUCHAR prx_tsc,
							 IN UCHAR key_type, IN UCHAR key_len, IN PUCHAR pkey_data )
{
	PWB35REG	pWb35Reg = &pHwData->Wb35Reg;
	PKEY_TABLE	pKey;
	PULONG		pltmp;
	ULONG		ltmp;
	UCHAR		Key_content[sizeof(KEY_TABLE)+ 16 + 8 ]; //16 bytes for key content, 8 bytes for burst writing
	UCHAR		i, j;
	PUCHAR		pValue;  //20060926 anson's endian

	if( pHwData->SurpriseRemove ) return FALSE;

	#ifdef _PE_STATE_DUMP_
	WBDEBUG(("hal mapping key set\n"));
	for( i=0; i<key_len; i++ )
		WBDEBUG(("%x ", pkey_data[i] ));
	WBDEBUG(("\n"));
	#endif

	// Turn off the reply ACK ability 930409.2
	// Due to DI-624. If user uses the WPA-PSK mode, driver doesn't
	// have enough time to setup the pairwise key into hardware.
	// For getting more time, disable the ACK ability to let the
	// AP retry to send the next packet which contains the group key data.
	pWb35Reg->M40_MacControl |= 0x4000;
	Wb35Reg_Write( pHwData, 0x0840, pWb35Reg->M40_MacControl );

	// Set key table contain
	OS_MEMORY_CLEAR( Key_content, sizeof(KEY_TABLE)+ 16 + 8 ); // 8 bytes for burst writing
	pKey = (PKEY_TABLE)(Key_content + 4 ); // Space 4 byte for burst command

	pValue = (UCHAR *)pKey;
	*pValue = 0x01;							//bit 0
	*pValue |= ((null_key ? 0: 1) << 1);	//bit 1, 35 hardware different with 33
	*pValue |= (key_type << 2);				//bit 2~3
	*pValue |= (wep_on << 4);				//bit 4
	pValue += 2;
    OS_MEMORY_COPY( pValue, pmac_addr, sizeof(USHORT) );	//addr 1

	OS_MEMORY_COPY( &(pKey->DW1_Address2), pmac_addr + 2, sizeof(ULONG) );

	if( prx_tsc )
     {
	
	
		pValue = (UCHAR *)pKey +8 ;  //20060926 anson's endian
		OS_MEMORY_COPY( pValue, prx_tsc, 6 ); //20060926 anson's endian
	}
	if( ptx_tsc )
	{
	
		pValue = (UCHAR *)pKey +16;   //20060926 anson's endian
		OS_MEMORY_COPY( pValue, ptx_tsc, 6 ); //20060926 anson's endian
	}
	//fill key content [20060623]
	OS_MEMORY_COPY( ((PUCHAR)pKey+sizeof(KEY_TABLE)), pkey_data, key_len );

	j = 0xff;
	for( i=MAPPING_KEY_START_INDEX; i<MAX_KEY_TABLE; i++ )
	{
	
		pValue = (UCHAR *)pKey + 2;  //20060926 anson's endian
		if ( OS_MEMORY_COMPARE(pValue, pHwData->Key_slot[i], 6) )  //20060926 anson's endian
		{
			pHwData->mapping_key_replace_index = i + 1;
			if( pHwData->mapping_key_replace_index == MAX_KEY_TABLE )
				pHwData->mapping_key_replace_index = MAPPING_KEY_START_INDEX;
			break;
		}

		if( OS_MEMORY_COMPARE( pHwData->Key_slot[i], "\x00\x00\x00\x00\x00\x00", MAC_ADDR_LENGTH ) )
			if( j == 0xff )
				j = i;//Storing the index which can be used
	}

	if( i == MAX_KEY_TABLE ) //Not found the entry, get one to use
	{
		if( j == 0xff )//Is out of resource? If yes, get an elder one index to be replaced
			i = pHwData->mapping_key_replace_index;
		else
			i = j;

		pHwData->mapping_key_replace_index = i + 1;
		if( pHwData->mapping_key_replace_index == MAX_KEY_TABLE )
			pHwData->mapping_key_replace_index = MAPPING_KEY_START_INDEX;

		//storing data
		//--- 20060926 anson's endian
		// *(PUSHORT)pHwData->Key_slot[i] = (USHORT)pKey->DW0_Address1; // @@
		//OS_MEMORY_COPY( pHwData->Key_slot[i] + 2, &(pKey->DW1_Address2), sizeof(ULONG) );
		pValue = (UCHAR *)pKey + 2;  //20060926 add by anson's endian
		OS_MEMORY_COPY( pHwData->Key_slot[i], pValue, 6); //20060926 add by anson's endian
	}

	// For new hardware supported. Using Burst register write
	#ifdef _PE_STATE_DUMP_
	WBDEBUG(("35: Key set start..\n"));
	#endif
	pltmp = (PULONG)Key_content;
	ltmp = i<<4;
	ltmp |= 0x4000000;
	pltmp[0] = ltmp; // Burst command
	pltmp[11] = pltmp[1]; // The last, valid bit set
	pltmp[1] = 0;// The first, clear the valid bit
	OS_MEMORY_COPY( pHwData->Key_content[i], pltmp, sizeof(ULONG)*12 ); // 20060214 for recover
        //--- 20060926 add by anson's endian
        pltmp[0] = cpu_to_le32( ltmp );
        for (i=0; i<=11; i++)
		pltmp[i] = cpu_to_le32( pltmp[i] );

        //--- end 20060926 add by anson's endian
	Wb35Reg_BurstWrite( pHwData, 0x881c, pltmp, 12, IGNORE_INCREMENT );

	// Turn on the reply ACK ability
	pWb35Reg->M40_MacControl &= ~0x4000;
	Wb35Reg_Write( pHwData, 0x0840, pWb35Reg->M40_MacControl );

	#ifdef _PE_STATE_DUMP_
	WBDEBUG(("hal_set_mapping_key[%d]\n", i));
	#endif

	return TRUE;
}
//---------------------------------------------------------------------------------------------------
BOOLEAN hal_set_default_key( phw_data_t pHwData, IN UCHAR index, IN UCHAR null_key,
							 IN UCHAR wep_on, IN PUCHAR ptx_tsc, IN PUCHAR prx_tsc,
							 IN UCHAR key_type, IN UCHAR key_len, IN PUCHAR pkey_data )
{
	PKEY_TABLE	pKey;
	PULONG		pltmp;
	ULONG		ltmp;
	UCHAR		Key_content[sizeof(KEY_TABLE)+ 16 + 8 ]; //16 bytes for key content, 8 bytes for burst writing
	PUCHAR		pValue;  //20060926 add by anson's endian  
	UCHAR		i;  //20060926 add by anson's endian

	if( pHwData->SurpriseRemove ) return FALSE;

	#ifdef _PE_STATE_DUMP_
	{
		int i;

		WBDEBUG(("hal default key set\n"));
		for( i=0; i<key_len; i++ )
			WBDEBUG(("%x ", pkey_data[i] ));
		WBDEBUG(("\n"));
	}
	#endif

	// Set key table contain
	OS_MEMORY_CLEAR( Key_content, sizeof(KEY_TABLE) + 16 + 8 ); // 8 bytes for burst writing
	pKey = (PKEY_TABLE)(Key_content + 4 );
//	//20060926 anson's endian
//	pKey->DW0_Valid = 1; // Valid bit
//	pKey->DW0_NullKey = null_key ? 0 : 1; // 35 hardware different with 33
//	pKey->DW0_Security_Mode = key_type;
//	pKey->DW0_WEPON = wep_on;
	pValue = (UCHAR *)pKey;
	*pValue = 0x01;							//bit 0
	*pValue |= ((null_key ? 0: 1) << 1);	//bit 1, 35 hardware different with 33
	*pValue |= (key_type << 2);				//bit 2~3
	*pValue |= (wep_on << 4);				//bit 4

	if( prx_tsc )
	{
               //20060926 anson's endian
		//pKey->DW2_RxSequenceCount1 = *(PULONG)prx_tsc; // 4n Alignment
		//pKey->DW3_RxSequenceCount2 = *(PUSHORT)(prx_tsc+4); // 2n Alignment
                pValue = (UCHAR *)pKey +8; //20060926 anson's endian
	        OS_MEMORY_COPY( pValue, prx_tsc, 6 ); //20060926 anson's endian
	}
	if( ptx_tsc )
	{
                //20060926 anson's endian
		//pKey->DW4_TxSequenceCount1 = *(PULONG)ptx_tsc; // 4n Alignment
		//pKey->DW5_TxSequenceCount2 = *(PUSHORT)(ptx_tsc+4); // 2n Alignment
                pValue = (UCHAR *)pKey+ 16; //20060926 anson's endian
                OS_MEMORY_COPY( pValue, ptx_tsc, 6 ); //20060926 anson's endian
	}
	//fill key content [20060623]
	OS_MEMORY_COPY( ((PUCHAR)pKey+sizeof(KEY_TABLE)), pkey_data, key_len );

	// 950301.3.a modify
	pHwData->CurrentDefaultKeyIndex = index;// Backup default key 941130.2
	pHwData->CurrentDefaultKeyLength = key_len;

	// For new hardware supported. Using Burst register write
	pltmp = (PULONG)Key_content;
	ltmp = index<<4;
		ltmp |= 0x4000000;
	
	pltmp[0] = ltmp; // Burst command
	pltmp[11] = pltmp[1]; // The last, valid bit set
	pltmp[1] = 0;// The first, clear the valid bit
	OS_MEMORY_COPY( pHwData->Key_content[index], pltmp, sizeof(ULONG)*12 ); // 20060214 for recover
        //---20060926 add by anson's endian
        pltmp[0] = cpu_to_le32( ltmp );  
        for( i=0; i<=11; i++)
               pltmp[i]=cpu_to_le32( pltmp[i]);
	//--- end 20060926 add by anson's endian
	Wb35Reg_BurstWrite( pHwData, 0x881c, pltmp, 12, IGNORE_INCREMENT );

	#ifdef _PE_STATE_DUMP_
	WBDEBUG(("hal_set_default_key[%d]\n", index));
	#endif

	return TRUE;
}
//---------------------------------------------------------------------------------------------------
VOID hal_clear_all_default_key( phw_data_t pHwData )
{
	ULONG	pltmp[GROUP_KEY_START_INDEX];
	UCHAR	i;

	if( pHwData->SurpriseRemove ) return;

	#ifdef _PE_STATE_DUMP_
	WBDEBUG(("hal_clear_all_default_key\n"));
	#endif

	// M20 KEY data, set to 0
	Wb35Reg_Write( pHwData, 0x0820, 0 );
	// M1c KEY write operation
	for( i=0; i<GROUP_KEY_START_INDEX; i++ )
	{
		pltmp[i] = i<<4;
		pltmp[i] |= 0x4000000;
	}
	Wb35Reg_BurstWrite( pHwData, 0x081c, pltmp, GROUP_KEY_START_INDEX, NO_INCREMENT );
	OS_MEMORY_CLEAR( pHwData->Key_slot[0], GROUP_KEY_START_INDEX*8 ); // 20060214 for recover
}
//---------------------------------------------------------------------------------------------------
VOID hal_clear_all_group_key( phw_data_t pHwData )
{
	ULONG	pltmp[MAPPING_KEY_START_INDEX-GROUP_KEY_START_INDEX];
	UCHAR	i;

	if( pHwData->SurpriseRemove ) return;

	#ifdef _PE_STATE_DUMP_
	WBDEBUG(("hal_clear_all_group_key\n"));
	#endif

	// M20 KEY data, set to 0
	Wb35Reg_Write( pHwData, 0x0820, 0 );
	// M1c KEY write operation
	for( i=GROUP_KEY_START_INDEX; i<MAPPING_KEY_START_INDEX; i++ )
	{
		pltmp[i-GROUP_KEY_START_INDEX] = i<<4;
		pltmp[i-GROUP_KEY_START_INDEX] |= 0x4000000;
	}
	Wb35Reg_BurstWrite( pHwData, 0x081c, pltmp, MAPPING_KEY_START_INDEX-GROUP_KEY_START_INDEX, NO_INCREMENT );
	OS_MEMORY_CLEAR( pHwData->Key_slot[GROUP_KEY_START_INDEX], (MAPPING_KEY_START_INDEX-GROUP_KEY_START_INDEX)*8 ); // 20060214 for recover
}
//---------------------------------------------------------------------------------------------------
VOID hal_clear_all_mapping_key( phw_data_t pHwData )
{
	ULONG	pltmp[MAX_KEY_TABLE-MAPPING_KEY_START_INDEX];
	UCHAR	i;

	if( pHwData->SurpriseRemove ) return;

	#ifdef _PE_STATE_DUMP_
	WBDEBUG(("hal_clear_all_mapping_key\n"));
	#endif

	// M20 KEY data, set to 0
	Wb35Reg_Write( pHwData, 0x0820, 0 );
	// M1c KEY write operation
	for( i=MAPPING_KEY_START_INDEX; i<MAX_KEY_TABLE; i++ )
	{
		pltmp[i-MAPPING_KEY_START_INDEX] = i<<4;
		pltmp[i-MAPPING_KEY_START_INDEX] |= 0x4000000;
	}
	Wb35Reg_BurstWrite( pHwData, 0x081c, pltmp, MAX_KEY_TABLE-MAPPING_KEY_START_INDEX, NO_INCREMENT );

	pHwData->mapping_key_replace_index = MAPPING_KEY_START_INDEX;
	OS_MEMORY_CLEAR( pHwData->Key_slot[MAPPING_KEY_START_INDEX], (MAX_KEY_TABLE-MAPPING_KEY_START_INDEX)*8 ); // Modify due to enlarge data struct 6 -> 8
}
//---------------------------------------------------------------------------------------------------
VOID hal_clear_all_key( phw_data_t pHwData )
{
	ULONG	pltmp[MAX_KEY_TABLE];
	UCHAR	i;

	if( pHwData->SurpriseRemove ) return;

	#ifdef _PE_STATE_DUMP_
	WBDEBUG(("hal_clear_all_key\n"));
	#endif

	// M20 KEY data, set to 0
	Wb35Reg_Write( pHwData, 0x0820, 0 );
	// M1c KEY write operation
	for( i=0; i<MAX_KEY_TABLE; i++ )
	{
		pltmp[i] = i<<4;
		pltmp[i] |= 0x4000000;
	}
	Wb35Reg_BurstWrite( pHwData, 0x081c, pltmp, 16, NO_INCREMENT );
	Wb35Reg_BurstWrite( pHwData, 0x081c, pltmp+16, MAX_KEY_TABLE-16, NO_INCREMENT );
	OS_MEMORY_CLEAR( pHwData->Key_slot[0], MAX_KEY_TABLE*8 ); // 20060214 for recover
}
//---------------------------------------------------------------------------------------------------
VOID hal_get_ethernet_address( phw_data_t pHwData, PUCHAR current_address )
{
	if( pHwData->SurpriseRemove ) return;

	OS_MEMORY_COPY( current_address, pHwData->CurrentMacAddress, ETH_LENGTH_OF_ADDRESS );
}
//---------------------------------------------------------------------------------------------------
VOID hal_set_ethernet_address( phw_data_t pHwData, PUCHAR current_address )
{
	ULONG ltmp[2];  //20060926 add by anson's endian

	if( pHwData->SurpriseRemove ) return;

	OS_MEMORY_COPY( pHwData->CurrentMacAddress, current_address, ETH_LENGTH_OF_ADDRESS );
	//--- 20060926 add by anson's endian
	ltmp[0]= cpu_to_le32( *(PULONG)pHwData->CurrentMacAddress );
	ltmp[1]= cpu_to_le32( *(PULONG)(pHwData->CurrentMacAddress + 4) ) & 0xffff;
	//--- end 20060926 add by anson's endia
	//Wb35Reg_BurstWrite( pHwData,0x03e8, (PULONG)pHwData->CurrentMacAddress, 2, AUTO_INCREMENT );
	Wb35Reg_BurstWrite( pHwData,0x03e8, ltmp, 2, AUTO_INCREMENT ); //20060926 add by anson's endian
}
//---------------------------------------------------------------------------------------------------
VOID hal_get_permanent_address( phw_data_t pHwData, PUCHAR pethernet_address )
{
	if( pHwData->SurpriseRemove ) return;

	OS_MEMORY_COPY( pethernet_address, pHwData->PermanentMacAddress, 6 );
}
//---------------------------------------------------------------------------------------------------
UCHAR hal_init_hardware( IN phw_data_t pHwData, IN PWB32_ADAPTER Adapter )
{
	USHORT SoftwareSet;
	pHwData->Adapter = Adapter;

	// Initial the variable
	pHwData->mapping_key_replace_index = MAPPING_KEY_START_INDEX; // Setting the default mapping key index
	pHwData->MaxReceiveLifeTime = DEFAULT_MSDU_LIFE_TIME; // Setting Rx maximum MSDU life time
	pHwData->FragmentThreshold = DEFAULT_FRAGMENT_THRESHOLD; // Setting default fragment threshold

	if( WbUsb_initial( pHwData ) )
	{
		pHwData->InitialResource = 1;
		if( Wb35Reg_initial( pHwData ) )
		{
			pHwData->InitialResource = 2;
			if( Wb35Tx_initial( pHwData ) )
			{
				pHwData->InitialResource = 3;
				if( Wb35Rx_initial( pHwData ) )
				{
					pHwData->InitialResource = 4;
					OS_TIMER_INITIAL( &pHwData->LEDTimer, hal_led_control, pHwData );
					OS_TIMER_SET( &pHwData->LEDTimer, 1000 ); // 20060623
					hal_clear_all_key( pHwData );//Because HW doesn't clear the WEP KEY table

					//
					// For restrict to vendor's hardware
					//
					SoftwareSet = hal_software_set( pHwData );

					#ifdef Vendor2
					// Try to make sure the EEPROM contain
					SoftwareSet >>= 8;
					if( SoftwareSet != 0x82 )
						return FALSE;
					#endif

					Wb35Rx_start( pHwData );
					Wb35Tx_EP2VM_start( pHwData );

					return TRUE;
				}
			}
		}
	}

	pHwData->SurpriseRemove = 1;
	return FALSE;
}
//---------------------------------------------------------------------------------------------------
VOID hal_halt( IN phw_data_t pHwData, IN void *ppa_data )
{
//	PADAPTER Adapter = pHwData->Adapter;
//	PWB35REG pWb35Reg = &pHwData->Wb35Reg;
//	BOOLEAN	cancel;

	switch( pHwData->InitialResource )
	{
		case 4:
		case 3: OS_TIMER_CANCEL( &pHwData->LEDTimer, &cancel );
				OS_SLEEP(100000); // Wait for Timer DPC exit 940623.2
				Wb35Rx_destroy( pHwData ); // Release the Rx
		case 2: Wb35Tx_destroy( pHwData ); // Release the Tx
		case 1: Wb35Reg_destroy( pHwData ); // Release the Wb35 Regisster resources
				WbUsb_destroy( pHwData );// Release the WbUsb
	}
}
//---------------------------------------------------------------------------------------------------
VOID
hal_set_power_save_mode( IN phw_data_t pHwData, IN BOOLEAN power_save, IN BOOLEAN wakeup, IN BOOLEAN dtim )
{
	PWB35REG	pWb35Reg = &pHwData->Wb35Reg;
	ULONG		Value;

	if( pHwData->SurpriseRemove ) return;

	// Power save setting
	//pHwData->desired_power_save = power_save;
	pWb35Reg->M24_MacControl &= ~0x0200c000;	//clear ps-poll and pwr active/save bits

	if( power_save )
	{
		pWb35Reg->M24_MacControl |= 0x02004000;	//enable ps-poll and pwr save
	}
	else
	{
		//if( pWb35Reg->mac_power_save )
		// Force MAC active
		pWb35Reg->M24_MacControl |= 0x8000;
		dtim = 0; // Reset dtim set
	}

	// Receive DTIM set
	pHwData->dtim = dtim;
	pWb35Reg->M24_MacControl &= ~0x00002000;
	if( pHwData->dtim )
		pWb35Reg->M24_MacControl |= 0x00002000;

	Value = pWb35Reg->M24_MacControl;
	//M24_MacControl should not record the bits FMACA(force active), FMACPS(force power save)
	//These h/w bits will be cleared after set. If the s/w M24_MacControl records them, other places
	//set M24 will set them again. The NULL packets will be sent by h/w.
	pWb35Reg->M24_MacControl &= ~0x0000c000;
	// Writing into M24
	Wb35Reg_Write( pHwData, 0x0824, Value );
}
//---------------------------------------------------------------------------------------------------
VOID hal_get_power_save_mode( IN phw_data_t pHwData, IN OUT PBOOLEAN pin_pwr_save )
{
	PWB35REG	pWb35Reg = &pHwData->Wb35Reg;

	if( pHwData->SurpriseRemove ) return;

	Wb35Reg_Read( pHwData, 0x084c, &pWb35Reg->M4C_MacStatus );
	pHwData->power_save_point = pin_pwr_save;
}
//---------------------------------------------------------------------------------------------------
VOID hal_set_slot_time( phw_data_t pHwData, IN UCHAR type )
{
	PWB35REG	pWb35Reg = &pHwData->Wb35Reg;

	if( pHwData->SurpriseRemove ) return;

	// Slot time setting
	pHwData->slot_time_select =  20; // default set to long
	pWb35Reg->M78_ERPInformation &= ~0x8; // the same setting in ERP
	if( WLAN_SLOT_TIME_TYPE_SHORT == type )
	{
		pHwData->slot_time_select =  9; // Set to short slot time
		pWb35Reg->M78_ERPInformation |= 0x8; // the sam setting in ERP
	}

	pWb35Reg->M40_MacControl &= ~0x3f;
	pWb35Reg->M40_MacControl |= pHwData->slot_time_select;
	Wb35Reg_Write( pHwData, 0x0840, pWb35Reg->M40_MacControl );

	Wb35Reg_Write( pHwData, 0x0878, pWb35Reg->M78_ERPInformation );
}
//---------------------------------------------------------------------------------------------------
VOID hal_set_rates( IN phw_data_t pHwData, IN PUCHAR pbss_rates, IN UCHAR length, IN BOOLEAN basic_rate_set )
{
	PWB35REG	pWb35Reg = &pHwData->Wb35Reg;
	ULONG		tmp, tmp1;
	UCHAR		Rate[12]={ 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 };
	UCHAR		SupportedRate[16];
	UCHAR		i, j, k, Count1, Count2, Byte;

	if( pHwData->SurpriseRemove ) return;

	if( basic_rate_set )
	{
		pWb35Reg->M28_MacControl &= ~0x000fff00;
		tmp1 = 0x00000100;
	}
	else
	{
		pWb35Reg->M28_MacControl &= ~0xfff00000;
		tmp1 = 0x00100000;
	}

	tmp = 0;
	for( i=0; i<length; i++ )
	{
		Byte = pbss_rates[i] & 0x7f;
		for( j=0; j<12; j++ )
		{
			if( Byte == Rate[j] )
				break;
		}

		if( j < 12 )
			tmp |= (tmp1<<j);
	}

	pWb35Reg->M28_MacControl |= tmp;
	Wb35Reg_Write( pHwData, 0x0828, pWb35Reg->M28_MacControl );

	// 930206.2.c M78 setting
	j = k = Count1 = Count2 = 0;
	OS_MEMORY_CLEAR( SupportedRate, 16 );
	tmp = 0x00100000;
	tmp1 = 0x00000100;
	for( i=0; i<12; i++ ) // Get the supproted rate
	{
		if( tmp & pWb35Reg->M28_MacControl )
		{
			SupportedRate[j] = Rate[i];

			if( tmp1 & pWb35Reg->M28_MacControl )
				SupportedRate[j] |= 0x80;

			if( k )
				Count2++;
			else
				Count1++;

			j++;
		}

		if( i==4 && k==0 )
		{
			if( !(pWb35Reg->M28_MacControl & 0x000ff000) ) // if basic rate in 11g domain)
			{
				k = 1;
				j = 8;
			}
		}

		tmp <<= 1;
		tmp1 <<= 1;
	}

	// Fill data into support rate until buffer full
	//---20060926 add by anson's endian
	for (i=0; i<4; i++)
	*(PULONG)(SupportedRate+(i<<2)) = cpu_to_le32( *(PULONG)(SupportedRate+(i<<2)) );
	//--- end 20060926 add by anson's endian
	Wb35Reg_BurstWrite( pHwData,0x087c, (PULONG)SupportedRate, 4, AUTO_INCREMENT );
	pWb35Reg->M7C_MacControl = ((PULONG)SupportedRate)[0];
	pWb35Reg->M80_MacControl = ((PULONG)SupportedRate)[1];
	pWb35Reg->M84_MacControl = ((PULONG)SupportedRate)[2];
	pWb35Reg->M88_MacControl = ((PULONG)SupportedRate)[3];

	// Fill length
	tmp = Count1<<28 | Count2<<24;
	pWb35Reg->M78_ERPInformation &= ~0xff000000;
	pWb35Reg->M78_ERPInformation |= tmp;
	Wb35Reg_Write( pHwData, 0x0878, pWb35Reg->M78_ERPInformation );
}
//---------------------------------------------------------------------------------------------------
VOID hal_start_bss( IN phw_data_t pHwData, IN UCHAR mac_op_mode )
{
	PWB35REG	pWb35Reg = &pHwData->Wb35Reg;

	if( pHwData->SurpriseRemove ) return;

	pHwData->bss_type = 1; // Default set to Infrastructure
	if( mac_op_mode == WLAN_BSSTYPE_INDEPENDENT )
		pHwData->bss_type = 0; // IBSS

	// Start bss
	pWb35Reg->M24_MacControl &= ~0xf0000000; // Clear the bit mask
	if( !pHwData->bss_type )
		pWb35Reg->M24_MacControl |= 0x40000000; //IBSS mode

	pWb35Reg->M24_MacControl |= 0x20000000; // Start BSS or IBSS bit
	Wb35Reg_Write( pHwData, 0x0824, pWb35Reg->M24_MacControl );
}
//---------------------------------------------------------------------------------------------------
VOID hal_join_request( IN phw_data_t pHwData, IN UCHAR bss_type )
{
	PWB35REG	pWb35Reg = &pHwData->Wb35Reg;
//	PWB32_ADAPTER Adapter=pHwData->Adapter;

	if( pHwData->SurpriseRemove ) return;

	pHwData->IsWaitJoinComplete = TRUE;

	pHwData->bss_type = 1; // Default set to Infrastructure

	if( bss_type == WLAN_BSSTYPE_INDEPENDENT )
		pHwData->bss_type = 0; // IBSS

	// Join BSS or IBSS request
	pWb35Reg->M24_MacControl &= ~0xf0000000; // Clear the bit mask
	if( !pHwData->bss_type )
		pWb35Reg->M24_MacControl |= 0x40000000; //IBSS mode

	pWb35Reg->M24_MacControl |= 0x10000000; // Join request bit
	Wb35Reg_Write( pHwData, 0x0824, pWb35Reg->M24_MacControl ); 

	#ifdef _PE_STATE_DUMP_
	WBDEBUG(("The join channel is %d\n", Adapter->sHwData.Channel));
	#endif
}
//---------------------------------------------------------------------------------------------------
VOID hal_stop_sync_bss( IN phw_data_t pHwData )
{
	PWB35REG	pWb35Reg = &pHwData->Wb35Reg;

	if( pHwData->SurpriseRemove ) return;

	pWb35Reg->M24_MacControl &= ~0x30000000; // clear STASS and JOR bits
	Wb35Reg_Write( pHwData, 0x0824, pWb35Reg->M24_MacControl );
}
//---------------------------------------------------------------------------------------------------
VOID hal_resume_sync_bss( IN phw_data_t pHwData)
{
	PWB35REG	pWb35Reg = &pHwData->Wb35Reg;

	if( pHwData->SurpriseRemove ) return;

	if (pHwData->bss_type == 1)	//infrastructure mode
		pWb35Reg->M24_MacControl |= 0x10000000;
	else
		pWb35Reg->M24_MacControl |= 0x20000000;	//IBSS mode alway use STASS
	Wb35Reg_Write( pHwData, 0x0824, pWb35Reg->M24_MacControl );
}
//---------------------------------------------------------------------------------------------------
VOID hal_set_aid( IN phw_data_t pHwData, IN USHORT aid )
{
	ULONG	tmp;

	if( pHwData->SurpriseRemove ) return;

	pHwData->AID = aid;
	tmp = pHwData->AID << 16;
	tmp |= cpu_to_le16( *(PUSHORT)(pHwData->bssid + 4) ); //20060926 anson's endian
	Wb35Reg_Write( pHwData, 0x0834, tmp );
}
//---------------------------------------------------------------------------------------------------
VOID hal_set_bssid( IN phw_data_t pHwData, IN PUCHAR pbssid )
{
	ULONG	pltmp[2];

	if( pHwData->SurpriseRemove ) return;

	OS_MEMORY_COPY( pHwData->bssid, pbssid, ETH_LENGTH_OF_ADDRESS );
	pltmp[0] = cpu_to_le32( *(PULONG)pHwData->bssid ); //20060926 anson's endian
	pltmp[1] = pHwData->AID << 16;
	pltmp[1] |=cpu_to_le16(*(PUSHORT)(pHwData->bssid + 4) );  //20060926 anson;s endian
	Wb35Reg_BurstWrite( pHwData, 0x0830, pltmp, 2, AUTO_INCREMENT );
}
//---------------------------------------------------------------------------------------------------
// Memory space pointer pbssid must be kept valid until hal_get_bssid_complete() fired
VOID hal_get_bssid( IN phw_data_t pHwData, IN PUCHAR pbssid )
{
	if( pHwData->SurpriseRemove ) return;

		Wb35Reg_Read( pHwData, 0x0834, (PULONG)(pHwData->bssid + 4));
		Wb35Reg_Read( pHwData, 0x0830, (PULONG)pHwData->bssid );
		pHwData->bssid_pointer = pbssid;
}
//---------------------------------------------------------------------------------------------------
VOID hal_set_beacon_period( IN phw_data_t pHwData, IN USHORT beacon_period )
{
	ULONG	tmp;

	if( pHwData->SurpriseRemove ) return;

	pHwData->BeaconPeriod = beacon_period;
	tmp = pHwData->BeaconPeriod << 16;
	tmp |= pHwData->ProbeDelay;
	Wb35Reg_Write( pHwData, 0x0848, tmp );
}
//---------------------------------------------------------------------------------------------------
VOID hal_set_listen_interval( IN phw_data_t pHwData, IN USHORT listen_interval )
{
	PWB35REG	pWb35Reg = &pHwData->Wb35Reg;
	ULONG		tmp;

	if( pHwData->SurpriseRemove ) return;

	pHwData->ListenInterval = listen_interval;
	pWb35Reg->M2C_MacControl &= 0x0000ffff;//Clear the origial value
	tmp = pHwData->ListenInterval << 16;
	pWb35Reg->M2C_MacControl |= tmp;
	Wb35Reg_Write( pHwData, 0x082c, pWb35Reg->M2C_MacControl );
}
//---------------------------------------------------------------------------------------------------
VOID hal_set_cap_info( IN phw_data_t pHwData, IN USHORT capability_info )
{
	PWB35REG	pWb35Reg = &pHwData->Wb35Reg;
	ULONG		tmp;

	if( pHwData->SurpriseRemove ) return;

	pHwData->CapabilityInformation = capability_info;
	pWb35Reg->M38_MacControl &= 0x0000ffff;//Clear the origial value
	tmp = pHwData->CapabilityInformation << 16;
	pWb35Reg->M38_MacControl |= tmp;
	Wb35Reg_Write( pHwData, 0x0838, pWb35Reg->M38_MacControl );
}
//---------------------------------------------------------------------------------------------------
VOID hal_set_ssid( IN phw_data_t pHwData, IN PUCHAR pssid, IN UCHAR ssid_len )
{
	PWB35REG	pWb35Reg = &pHwData->Wb35Reg;
	ULONG		pltmp[9]; // 1 burst command + 8 DW SSID max
	ULONG		tmp;
	UCHAR		i, j;

	if( pHwData->SurpriseRemove ) return;

	OS_MEMORY_COPY( pHwData->ssid, pssid, ssid_len );
	OS_MEMORY_CLEAR( (PUCHAR)pltmp, 36 );
	//NOTE [WK endian]: ssid values will be tranfered by cpu_to_le32 in Wb35Reg_BurstWrite().
	//			 The ssid values must be tranfered first but burst cmd is not necessary.
	//OS_MEMORY_COPY( (PUCHAR)(pltmp+1), pssid, ssid_len );
	
	pHwData->ssid_length = ssid_len;

	j = (pHwData->ssid_length + 3) & ~0x03;
	j >>= 2;
	j += 1;// 1 DW burst command
	pltmp[0] = 0x10000000; // burst ssid command
	//[WK endian] 
	for (i= 1; i<j; i++)
		pltmp[i] = cpu_to_le32( *(PULONG)(pssid + ((i-1)<<2)) );
	Wb35Reg_BurstWrite( pHwData,0x881c, pltmp, j, AUTO_INCREMENT );

	// SSID length setting
	pWb35Reg->M4C_MacStatus &= ~0x003f0000;
	tmp = pHwData->ssid_length << 16;
	pWb35Reg->M4C_MacStatus |= tmp;
	Wb35Reg_Write( pHwData, 0x084c, pWb35Reg->M4C_MacStatus );
}
//---------------------------------------------------------------------------------------------------
VOID hal_set_current_channel_ex( IN phw_data_t pHwData, IN ChanInfo channel )
{
	PWB35REG pWb35Reg = &pHwData->Wb35Reg;

	if( pHwData->SurpriseRemove ) return;

	RFSynthesizer_SwitchingChannel( pHwData, channel );// Switch channel
	pHwData->Channel = channel.ChanNo;
	pHwData->band = channel.band;
	#ifdef _PE_STATE_DUMP_
	WBDEBUG(("Set channel is %d, band =%d\n", pHwData->Channel, pHwData->band));
	#endif
	pWb35Reg->M28_MacControl &= ~0xff; // Clean channel information field
	pWb35Reg->M28_MacControl |= channel.ChanNo;
	//Wb35Reg_Write( pHwData, 0x0828, pWb35Reg->M28_MacControl );// Writing Channel information
	Wb35Reg_WriteWithCallbackValue( pHwData, 0x0828, pWb35Reg->M28_MacControl,
									(PCHAR)&channel, sizeof(ChanInfo));
}
//---------------------------------------------------------------------------------------------------
VOID hal_set_current_channel( IN phw_data_t pHwData, IN ChanInfo channel )
{
	PADAPTER	Adapter = pHwData->Adapter;
//	PTESTSTA	pTestSta = &Adapter->sTestSta;

	if( TS_RUNNING_IN_TESTSTA_MODE )
		return; // Ignore setting if access right is not owned by NDIS

	hal_set_current_channel_ex( pHwData, channel );
}
//---------------------------------------------------------------------------------------------------
VOID hal_get_current_channel( IN phw_data_t pHwData, OUT ChanInfo *channel )
{
	channel->ChanNo = pHwData->Channel;
	channel->band = pHwData->band;
}
//---------------------------------------------------------------------------------------------------
VOID hal_set_accept_broadcast( IN phw_data_t pHwData, IN UCHAR enable )
{
	PWB35REG	pWb35Reg = &pHwData->Wb35Reg;

	if( pHwData->SurpriseRemove ) return;

	pWb35Reg->M00_MacControl &= ~0x02000000;//The HW value
	
	if( enable ) pWb35Reg->M00_MacControl |= 0x02000000;//The HW value
	
    
	Wb35Reg_Write( pHwData, 0x0800, pWb35Reg->M00_MacControl );
}
//---------------------------------------------------------------------------------------------------
//for wep key error detection, we need to accept broadcast packets to be received temporary.
void hal_set_accept_promiscuous(IN phw_data_t pHwData, IN UCHAR enable)
{   
	PWB35REG	pWb35Reg = &pHwData->Wb35Reg;

	if( pHwData->SurpriseRemove ) return;
	if(enable)
	{
		pWb35Reg->M00_MacControl |= 0x00400000;
		Wb35Reg_Write( pHwData, 0x0800, pWb35Reg->M00_MacControl );
	}
	else
	{
		pWb35Reg->M00_MacControl&=~0x00400000;
		Wb35Reg_Write( pHwData, 0x0800, pWb35Reg->M00_MacControl );
	}
}
//---------------------------------------------------------------------------------------------------
VOID hal_set_accept_multicast( IN phw_data_t pHwData, IN UCHAR enable )
{
	PWB35REG	pWb35Reg = &pHwData->Wb35Reg;

	if( pHwData->SurpriseRemove ) return;

	pWb35Reg->M00_MacControl &= ~0x01000000;//The HW value
	if( enable ) pWb35Reg->M00_MacControl |= 0x01000000;//The HW value
	Wb35Reg_Write( pHwData, 0x0800, pWb35Reg->M00_MacControl );
}
//---------------------------------------------------------------------------------------------------
VOID hal_set_accept_beacon( IN phw_data_t pHwData, IN UCHAR enable )
{
	PWB35REG	pWb35Reg = &pHwData->Wb35Reg;

	if( pHwData->SurpriseRemove ) return;

	// 20040108 debug
	if( !enable )//Due to SME and MLME are not suitable for 35
		return;

	pWb35Reg->M00_MacControl &= ~0x04000000;//The HW value
	if( enable )
		pWb35Reg->M00_MacControl |= 0x04000000;//The HW value

	Wb35Reg_Write( pHwData, 0x0800, pWb35Reg->M00_MacControl );
}
//---------------------------------------------------------------------------------------------------
VOID hal_set_multicast_address( phw_data_t pHwData, PUCHAR address, UCHAR number )
{
	PWB35REG	pWb35Reg = &pHwData->Wb35Reg;
	UCHAR		Byte, Bit;

	if( pHwData->SurpriseRemove ) return;

	//Erases and refills the card multicast registers. Used when an address
	//    has been deleted and all bits must be recomputed.
	pWb35Reg->M04_MulticastAddress1 = 0;
	pWb35Reg->M08_MulticastAddress2 = 0;

	while( number )
	{
		number--;
		CardGetMulticastBit( (address+(number*ETH_LENGTH_OF_ADDRESS)), &Byte, &Bit);
		pWb35Reg->Multicast[Byte] |= Bit;
	}

	// Updating register
	Wb35Reg_BurstWrite( pHwData, 0x0804, (PULONG)pWb35Reg->Multicast, 2, AUTO_INCREMENT );
}
//---------------------------------------------------------------------------------------------------
UCHAR hal_get_accept_beacon( IN phw_data_t pHwData )
{
	PWB35REG pWb35Reg = &pHwData->Wb35Reg;

	if( pHwData->SurpriseRemove ) return 0;

	if( pWb35Reg->M00_MacControl & 0x04000000 )
		return 1;
	else
		return 0;
}
//---------------------------------------------------------------------------------------------------
BOOLEAN hal_reset_hardware( phw_data_t pHwData, PVOID ppa )
{
	// Not implement yet
	return TRUE;
}
//---------------------------------------------------------------------------------------------------
VOID hal_stop( IN phw_data_t pHwData )
{
	PWB35REG	pWb35Reg = &pHwData->Wb35Reg;

	pHwData->Wb35Rx.rx_halt = 1; // 20051222.3 Move here for supriseremove
	Wb35Rx_stop( pHwData );

	pHwData->Wb35Tx.tx_halt = 1;
	Wb35Tx_stop( pHwData );

//	if( pHwData->SurpriseRemove ) return;

	pWb35Reg->D00_DmaControl &= ~0xc0000000;//Tx Off, Rx Off
	Wb35Reg_Write( pHwData, 0x0400, pWb35Reg->D00_DmaControl );

	WbUsb_Stop( pHwData ); // 20051230 Add.4
}
//---------------------------------------------------------------------------------------------------
BOOLEAN	hal_idle( IN phw_data_t pHwData )
{
	PWB35REG	pWb35Reg = &pHwData->Wb35Reg;
	PWBUSB	pWbUsb = &pHwData->WbUsb;

	if( !pHwData->SurpriseRemove && ( pWbUsb->DetectCount || pWb35Reg->EP0vm_state!=VM_STOP ) )
		return FALSE;

	return TRUE;
}
//---------------------------------------------------------------------------------------------------
VOID hal_set_cwmin( IN phw_data_t pHwData, IN UCHAR	cwin_min )
{
	PWB35REG	pWb35Reg = &pHwData->Wb35Reg;

	if( pHwData->SurpriseRemove ) return;

	pHwData->cwmin = cwin_min;
	pWb35Reg->M2C_MacControl &= ~0x7c00;	//bit 10 ~ 14
	pWb35Reg->M2C_MacControl |= (pHwData->cwmin<<10);
	Wb35Reg_Write( pHwData, 0x082c, pWb35Reg->M2C_MacControl );
}
//---------------------------------------------------------------------------------------------------
VOID hal_set_cwmax( IN phw_data_t pHwData, IN USHORT cwin_max )
{
	PWB35REG	pWb35Reg = &pHwData->Wb35Reg;

	if( pHwData->SurpriseRemove ) return;

	pHwData->cwmax = cwin_max;
	pWb35Reg->M2C_MacControl &= ~0x3ff;	//bit 0 ~ 9
	pWb35Reg->M2C_MacControl |= pHwData->cwmax;
	Wb35Reg_Write( pHwData, 0x082c, pWb35Reg->M2C_MacControl );
}
//----------------------------------------------------------------------------------------------------
VOID hal_set_rsn_wpa( IN phw_data_t pHwData, IN ULONG * RSN_IE_Bitmap ,IN ULONG * RSN_OUI_type, IN unsigned char bDesiredAuthMode)
{
    PWB35REG	pWb35Reg = &pHwData->Wb35Reg;
	ULONG		pltmp[2];

	if( pHwData->SurpriseRemove ) return;

	#ifdef _PE_STATE_DUMP_
    WBDEBUG(("[WS]hal_set_rsn_wpa\n"));
    WBDEBUG(("[WS]hal_RSN_IE_Bitmap=%x\n",*RSN_IE_Bitmap));
    WBDEBUG(("[WS]hal_RSN_OUI_type=%x\n",*RSN_OUI_type));
	#endif

    pWb35Reg->M24_MacControl &= ~0x500000;
    switch (bDesiredAuthMode)
	{
		case OPEN_AUTH:
		case SHARE_AUTH:break;

	    case WPA_AUTH:
		case WPAPSK_AUTH:
		case WPANONE_AUTH:
			pWb35Reg->M24_MacControl |= 0x500000;
			break;
        #ifdef _WPA2_
	    case WPA2_AUTH:
		case WPA2PSK_AUTH:
			pWb35Reg->M24_MacControl |= 0x100000;
			break;
        #endif //_WPA2_
        
		default:
			break;
	}
	Wb35Reg_Write( pHwData, 0x0824, pWb35Reg->M24_MacControl );

    //pWb35Reg->M24_MacControl = 0x00140042;
	OS_MEMORY_COPY( &pltmp[0], RSN_IE_Bitmap, sizeof(ULONG) );
	OS_MEMORY_COPY( &pltmp[1], RSN_OUI_type, sizeof(ULONG) );
	pWb35Reg->M70_MacControl = pltmp[0];
	pWb35Reg->M74_MacControl = pltmp[1];
	Wb35Reg_BurstWrite( pHwData, 0x0870, pltmp, 2, AUTO_INCREMENT );
}
//----------------------------------------------------------------------------------------------------
//LONG hal_get_rssi( IN phw_data_t pHwData, IN ULONG HalRssi )
LONG hal_get_rssi( IN phw_data_t pHwData, IN ULONG *HalRssiArry, IN u8 Count )
{
	PWB35REG pWb35Reg = &pHwData->Wb35Reg;
	R01_DESCRIPTOR	r01;
	LONG ltmp = 0, tmp;
	u8	i;

	if( pHwData->SurpriseRemove ) return -200;
	if( Count > MAX_ACC_RSSI_COUNT ) // Because the TS may use this funtion
		Count = MAX_ACC_RSSI_COUNT;

	// RSSI = C1 + C2 * (agc_state[7:0] + offset_map(lna_state[1:0]))
	// C1 = -195, C2 = 0.66 = 85/128
	for (i=0; i<Count; i++)
	{
		r01.value = HalRssiArry[i];
		tmp = ((( r01.R01_AGC_state + pWb35Reg->LNAValue[r01.R01_LNA_state]) * 85 ) >>7 ) - 195;
		ltmp += tmp;
	}
	ltmp /= Count;
	if( pHwData->phy_type == RF_AIROHA_2230 ) ltmp -= 5; // 10;
	if( pHwData->phy_type == RF_AIROHA_2230S ) ltmp -= 5; // 10; 20060420 Add this

	//if( ltmp < -200 ) ltmp = -200;
	if( ltmp < -110 ) ltmp = -110;// 1.0.24.0 For NJRC

	return ltmp;
}
//----------------------------------------------------------------------------------------------------
LONG hal_get_rssi_bss( IN phw_data_t pHwData, IN USHORT idx, IN u8 Count )
{
	PWB35REG pWb35Reg = &pHwData->Wb35Reg;
	R01_DESCRIPTOR	r01;
	LONG ltmp = 0, tmp;
	u8	i, j;
	PADAPTER	Adapter = pHwData->Adapter;
//	ULONG *HalRssiArry = psBSS(idx)->HalRssi;

	if( pHwData->SurpriseRemove ) return -200;
	if( Count > MAX_ACC_RSSI_COUNT ) // Because the TS may use this funtion
		Count = MAX_ACC_RSSI_COUNT;

	// RSSI = C1 + C2 * (agc_state[7:0] + offset_map(lna_state[1:0]))
	// C1 = -195, C2 = 0.66 = 85/128
#if 0
	for (i=0; i<Count; i++)
	{
		r01.value = HalRssiArry[i];
		tmp = ((( r01.R01_AGC_state + pWb35Reg->LNAValue[r01.R01_LNA_state]) * 85 ) >>7 ) - 195;
		ltmp += tmp;
	}
#else
	if (psBSS(idx)->HalRssiIndex == 0)
		psBSS(idx)->HalRssiIndex = MAX_ACC_RSSI_COUNT;
	j = (u8)psBSS(idx)->HalRssiIndex-1;

	for (i=0; i<Count; i++)
	{
		r01.value = psBSS(idx)->HalRssi[j];
		tmp = ((( r01.R01_AGC_state + pWb35Reg->LNAValue[r01.R01_LNA_state]) * 85 ) >>7 ) - 195;
		ltmp += tmp;
		if (j == 0)
		{
			j = MAX_ACC_RSSI_COUNT;
		}
		j--;
	}
#endif
	ltmp /= Count;
	if( pHwData->phy_type == RF_AIROHA_2230 ) ltmp -= 5; // 10;
	if( pHwData->phy_type == RF_AIROHA_2230S ) ltmp -= 5; // 10; 20060420 Add this

	//if( ltmp < -200 ) ltmp = -200;
	if( ltmp < -110 ) ltmp = -110;// 1.0.24.0 For NJRC

	return ltmp;
}
//----------------------------------------------------------------------------------------------------
//Info the hardware connection or disconnection
VOID hal_set_connect_info( IN phw_data_t pHwData, IN BOOLEAN boConnect )
{
	if( pHwData->SurpriseRemove ) return;

	if( boConnect )
	{
		pHwData->LED_LinkOn = 1;
		pHwData->NullPacketCount = 0;
	}
	else
		pHwData->LED_LinkOn = 0;
}
//----------------------------------------------------------------------------------------------------
VOID hal_led_control_1a( IN phw_data_t pHwData )
{
	hal_led_control( NULL, pHwData, NULL, NULL );
}
VOID hal_led_control( IN PVOID S1, IN phw_data_t pHwData, IN PVOID S3, IN PVOID S4 )
{
	PADAPTER	Adapter = pHwData->Adapter;
	PWB35REG	pWb35Reg = &pHwData->Wb35Reg;
//	PTESTSTA	pTestSta = &Adapter->sTestSta;
	ULONG	LEDSet = (pHwData->SoftwareSet & HAL_LED_SET_MASK) >> HAL_LED_SET_SHIFT;
	UCHAR	LEDgray[20] = { 0,3,4,6,8,10,11,12,13,14,15,14,13,12,11,10,8,6,4,2 };
	UCHAR	LEDgray2[30] = { 7,8,9,10,11,12,13,14,15,0,0,0,0,0,0,0,0,0,0,0,0,0,15,14,13,12,11,10,9,8 };
	ULONG	TimeInterval = 500, ltmp, ltmp2;
        ltmp=0;

	if( pHwData->SurpriseRemove ) return;

	if( pHwData->LED_control )
	{
		ltmp2 = pHwData->LED_control & 0xff;
		if( ltmp2 < 5 ) // 1 ~ 4 is TS mode
		{
			Ts_Led_Control( Adapter );
			TimeInterval = 20;
		}
		else if( ltmp2 == 5 ) // 5 is WPS mode
		{
			TimeInterval = 100;
			ltmp2 = (pHwData->LED_control>>8) & 0xff;
			switch( ltmp2 )
			{
				case 1: // [0.2 On][0.1 Off]...
					pHwData->LED_Blinking %= 3;
					ltmp = 0x1010; // Led 1 & 0 Green and Red
					if( pHwData->LED_Blinking == 2 ) // Turn off
						ltmp = 0;
					break;
				case 2: // [0.1 On][0.1 Off]...
					pHwData->LED_Blinking %= 2;
					ltmp = 0x0010; // Led 0 red color
					if( pHwData->LED_Blinking ) // Turn off
						ltmp = 0;
					break;
				case 3: // [0.1 On][0.1 Off][0.1 On][0.1 Off][0.1 On][0.1 Off][0.1 On][0.1 Off][0.1 On][0.1 Off][0.5 Off]...
					pHwData->LED_Blinking %= 15;
					ltmp = 0x0010; // Led 0 red color
					if( (pHwData->LED_Blinking >= 9) || (pHwData->LED_Blinking%2) ) // Turn off 0.6 sec
						ltmp = 0;
					break;
				case 4: // [300 On][ off ]
					ltmp = 0x1000; // Led 1 Green color
					if( pHwData->LED_Blinking >= 3000 )
						ltmp = 0; // led maybe on after 300sec * 32bit counter overlap.
					break;
			}
			pHwData->LED_Blinking++;

			pWb35Reg->U1BC_LEDConfigure = ltmp;
			if( LEDSet != 7 ) // Only 111 mode has 2 LEDs on PCB.
			{
				pWb35Reg->U1BC_LEDConfigure |= (ltmp &0xff)<<8; // Copy LED result to each LED control register
				pWb35Reg->U1BC_LEDConfigure |= (ltmp &0xff00)>>8;
			}
			Wb35Reg_Write( pHwData, 0x03bc, pWb35Reg->U1BC_LEDConfigure );
		}
	}
	else if( pHwData->CurrentRadioSw || pHwData->CurrentRadioHw ) // If radio off
	{
		if( pWb35Reg->U1BC_LEDConfigure & 0x1010 )
		{
			pWb35Reg->U1BC_LEDConfigure &= ~0x1010;
			Wb35Reg_Write( pHwData, 0x03bc, pWb35Reg->U1BC_LEDConfigure );
		}
	}
	else
	{
		switch( LEDSet )
		{
			case 4: // [100] Only 1 Led be placed on PCB and use pin 21 of IC. Use LED_0 for showing
				if( !pHwData->LED_LinkOn ) // Blink only if not Link On
				{
					// Blinking if scanning is on progress
					if( pHwData->LED_Scanning )
					{
						if( pHwData->LED_Blinking == 0 )
						{
							pWb35Reg->U1BC_LEDConfigure |= 0x10;
							Wb35Reg_Write( pHwData, 0x03bc, pWb35Reg->U1BC_LEDConfigure ); // LED_0 On
							pHwData->LED_Blinking = 1;
							TimeInterval = 300;
						}
						else
						{
							pWb35Reg->U1BC_LEDConfigure &= ~0x10;
							Wb35Reg_Write( pHwData, 0x03bc, pWb35Reg->U1BC_LEDConfigure ); // LED_0 Off
							pHwData->LED_Blinking = 0;
							TimeInterval = 300;
						}
					}
					else
					{
						//Turn Off LED_0
						if( pWb35Reg->U1BC_LEDConfigure & 0x10 )
						{
							pWb35Reg->U1BC_LEDConfigure &= ~0x10;
							Wb35Reg_Write( pHwData, 0x03bc, pWb35Reg->U1BC_LEDConfigure ); // LED_0 Off
						}
					}
				}
				else
				{
					// Turn On LED_0
					if( (pWb35Reg->U1BC_LEDConfigure & 0x10) == 0 )
					{
						pWb35Reg->U1BC_LEDConfigure |= 0x10;
						Wb35Reg_Write( pHwData, 0x03bc, pWb35Reg->U1BC_LEDConfigure ); // LED_0 Off
					}
				}
				break;

			case 6: // [110] Only 1 Led be placed on PCB and use pin 21 of IC. Use LED_0 for showing
				if( !pHwData->LED_LinkOn ) // Blink only if not Link On
				{
					// Blinking if scanning is on progress
					if( pHwData->LED_Scanning )
					{
						if( pHwData->LED_Blinking == 0 )
						{
							pWb35Reg->U1BC_LEDConfigure &= ~0xf;
							pWb35Reg->U1BC_LEDConfigure |= 0x10;
							Wb35Reg_Write( pHwData, 0x03bc, pWb35Reg->U1BC_LEDConfigure ); // LED_0 On
							pHwData->LED_Blinking = 1;
							TimeInterval = 300;
						}
						else
						{
							pWb35Reg->U1BC_LEDConfigure &= ~0x1f;
							Wb35Reg_Write( pHwData, 0x03bc, pWb35Reg->U1BC_LEDConfigure ); // LED_0 Off
							pHwData->LED_Blinking = 0;
							TimeInterval = 300;
						}
					}
					else
					{
						// 20060901 Gray blinking if in disconnect state and not scanning
						ltmp = pWb35Reg->U1BC_LEDConfigure;
						pWb35Reg->U1BC_LEDConfigure &= ~0x1f;
						if( LEDgray2[(pHwData->LED_Blinking%30)] )
						{
							pWb35Reg->U1BC_LEDConfigure |= 0x10;
							pWb35Reg->U1BC_LEDConfigure |= LEDgray2[ (pHwData->LED_Blinking%30) ];
						}
						pHwData->LED_Blinking++;
						if( pWb35Reg->U1BC_LEDConfigure != ltmp )
							Wb35Reg_Write( pHwData, 0x03bc, pWb35Reg->U1BC_LEDConfigure ); // LED_0 Off
						TimeInterval = 100;
					}
				}
				else
				{
					// Turn On LED_0
					if( (pWb35Reg->U1BC_LEDConfigure & 0x10) == 0 )
					{
						pWb35Reg->U1BC_LEDConfigure |= 0x10;
						Wb35Reg_Write( pHwData, 0x03bc, pWb35Reg->U1BC_LEDConfigure ); // LED_0 Off
					}
				}
				break;

			case 5: // [101] Only 1 Led be placed on PCB and use LED_1 for showing
				if( !pHwData->LED_LinkOn ) // Blink only if not Link On
				{
					// Blinking if scanning is on progress
					if( pHwData->LED_Scanning )
					{
						if( pHwData->LED_Blinking == 0 )
						{
							pWb35Reg->U1BC_LEDConfigure |= 0x1000;
							Wb35Reg_Write( pHwData, 0x03bc, pWb35Reg->U1BC_LEDConfigure ); // LED_1 On
							pHwData->LED_Blinking = 1;
							TimeInterval = 300;
						}
						else
						{
							pWb35Reg->U1BC_LEDConfigure &= ~0x1000;
							Wb35Reg_Write( pHwData, 0x03bc, pWb35Reg->U1BC_LEDConfigure ); // LED_1 Off
							pHwData->LED_Blinking = 0;
							TimeInterval = 300;
						}
					}
					else
					{
						//Turn Off LED_1
						if( pWb35Reg->U1BC_LEDConfigure & 0x1000 )
						{
							pWb35Reg->U1BC_LEDConfigure &= ~0x1000;
							Wb35Reg_Write( pHwData, 0x03bc, pWb35Reg->U1BC_LEDConfigure ); // LED_1 Off
						}
					}
				}
				else
				{
					// Is transmitting/receiving ??
					if( (OS_CURRENT_RX_BYTE( Adapter ) != pHwData->RxByteCountLast ) ||
						(OS_CURRENT_TX_BYTE( Adapter ) != pHwData->TxByteCountLast ) )
					{
						if( (pWb35Reg->U1BC_LEDConfigure & 0x3000) != 0x3000 )
						{
							pWb35Reg->U1BC_LEDConfigure |= 0x3000;
							Wb35Reg_Write( pHwData, 0x03bc, pWb35Reg->U1BC_LEDConfigure ); // LED_1 On
						}

						// Update variable
						pHwData->RxByteCountLast = OS_CURRENT_RX_BYTE( Adapter );
						pHwData->TxByteCountLast = OS_CURRENT_TX_BYTE( Adapter );
						TimeInterval = 200;
					}
					else
					{
						// Turn On LED_1 and blinking if transmitting/receiving
						 if( (pWb35Reg->U1BC_LEDConfigure & 0x3000) != 0x1000 )
						 {
							 pWb35Reg->U1BC_LEDConfigure &= ~0x3000;
							 pWb35Reg->U1BC_LEDConfigure |= 0x1000;
							 Wb35Reg_Write( pHwData, 0x03bc, pWb35Reg->U1BC_LEDConfigure ); // LED_1 On
						 }
					}
				}
				break;

			default: // Default setting. 2 LED be placed on PCB. LED_0: Link On LED_1 Active
				if( (pWb35Reg->U1BC_LEDConfigure & 0x3000) != 0x3000 )
				{
					pWb35Reg->U1BC_LEDConfigure |= 0x3000;// LED_1 is always on and event enable
					Wb35Reg_Write( pHwData, 0x03bc, pWb35Reg->U1BC_LEDConfigure );
				}

				if( pHwData->LED_Blinking )
				{
					// Gray blinking
					pWb35Reg->U1BC_LEDConfigure &= ~0x0f;
					pWb35Reg->U1BC_LEDConfigure |= 0x10;
					pWb35Reg->U1BC_LEDConfigure |= LEDgray[ (pHwData->LED_Blinking-1)%20 ];
					Wb35Reg_Write( pHwData, 0x03bc, pWb35Reg->U1BC_LEDConfigure );

					pHwData->LED_Blinking += 2;
					if( pHwData->LED_Blinking < 40 )
						TimeInterval = 100;
					else
					{
						pHwData->LED_Blinking = 0; // Stop blinking
						pWb35Reg->U1BC_LEDConfigure &= ~0x0f;
						Wb35Reg_Write( pHwData, 0x03bc, pWb35Reg->U1BC_LEDConfigure );
					}
					break;
				}

				if( pHwData->LED_LinkOn )
				{
					if( !(pWb35Reg->U1BC_LEDConfigure & 0x10) ) // Check the LED_0
					{
						//Try to turn ON LED_0 after gray blinking
						pWb35Reg->U1BC_LEDConfigure |= 0x10;
						pHwData->LED_Blinking = 1; //Start blinking
						TimeInterval = 50;
					}
				}
				else
				{
					if( pWb35Reg->U1BC_LEDConfigure & 0x10 ) // Check the LED_0
					{
						pWb35Reg->U1BC_LEDConfigure &= ~0x10;
						Wb35Reg_Write( pHwData, 0x03bc, pWb35Reg->U1BC_LEDConfigure );
					}
				}
				break;
		}

		//20060828.1 Active send null packet to avoid AP disconnect
		if( pHwData->LED_LinkOn )
		{
			pHwData->NullPacketCount += TimeInterval;
			if( pHwData->NullPacketCount >= DEFAULT_NULL_PACKET_COUNT )
			{
				SME_SEND_NULL_PACKET( Adapter,PWR_ACTIVE );
				pHwData->NullPacketCount = 0;
			}
		}
	}

	pHwData->time_count += TimeInterval;
	Wb35Tx_CurrentTime( pHwData, pHwData->time_count ); // 20060928 add
	OS_TIMER_SET( &pHwData->LEDTimer, TimeInterval ); // 20060623.1
}
//----------------------------------------------------------------------------------------------------
UCHAR hal_get_est_sq3( IN phw_data_t pHwData, UCHAR Count )
{
	PWB35REG	pWb35Reg = &pHwData->Wb35Reg;
	ULONG		ltmp = 0, i;

	if( pHwData->SurpriseRemove ) return 0;

	if( pWb35Reg->BB50 & 0xe0 )
	{
		pWb35Reg->BB50 &= ~0xe0;	//EST_SQ3
		Wb35Reg_Write( pHwData, 0x1050, pWb35Reg->BB50 );
	}

	Wb35Reg_Read( pHwData, 0x1060, &pWb35Reg->BB60 );

	if( Count > MAX_SQ3_FILTER_SIZE )
		Count = MAX_SQ3_FILTER_SIZE;
	pWb35Reg->SQ3_filter[ pWb35Reg->SQ3_index ] = pWb35Reg->BB60 & 0x7f;
	pWb35Reg->SQ3_index++;
	pWb35Reg->SQ3_index %= Count;

	for( i=0; i<Count; i++ )
		ltmp += pWb35Reg->SQ3_filter[i];

	return (UCHAR)(ltmp/Count);
}
//----------------------------------------------------------------------------------------------------
VOID hal_set_phy_type( IN phw_data_t pHwData, IN UCHAR PhyType )
{
	pHwData->phy_type = PhyType;
}
//----------------------------------------------------------------------------------------------------
VOID hal_get_phy_type( IN phw_data_t pHwData, IN UCHAR *PhyType )
{
	*PhyType = pHwData->phy_type;
}
//----------------------------------------------------------------------------------------------------
VOID hal_reset_counter( IN phw_data_t pHwData )
{
	pHwData->dto_tx_retry_count = 0;
	pHwData->dto_tx_frag_count = 0;
	memset( pHwData->tx_retry_count, 0, 8);
}
//----------------------------------------------------------------------------------------------------
//boValue = 1 : radio off
//			0 : radio on
VOID hal_set_radio_mode(IN phw_data_t pHwData, IN BOOLEAN boValue)
{
	PWB35REG	pWb35Reg = &pHwData->Wb35Reg;

	if( pHwData->SurpriseRemove ) return;

	if (boValue)	//disable Baseband receive off
	{
		pHwData->CurrentRadioSw = 1; // off
		pWb35Reg->M24_MacControl &= 0xffffffbf;
	}
	else
	{
		pHwData->CurrentRadioSw = 0; // on
		pWb35Reg->M24_MacControl |= 0x00000040;
	}
	Wb35Reg_Write( pHwData, 0x0824, pWb35Reg->M24_MacControl );
}
//----------------------------------------------------------------------------------------------------
VOID hal_descriptor_indicate( IN phw_data_t pHwData, IN PDESCRIPTOR pRxDes )
{
	PADAPTER Adapter = pHwData->Adapter;
//	PWB35REG	pWb35Reg = &pHwData->Wb35Reg;

	if( !pHwData->IsInitOK ) // 20060717.3 Add
		return;

	if( TS_RUNNING_IN_TESTSTA_MODE )
		{ TS_MpduProcess( Adapter, pRxDes ); }
	else
		{ Mds_MpduProcess( Adapter, pRxDes ); }
}

//----------------------------------------------------------------------------------------------------
u8 hal_get_antenna_number( IN phw_data_t pHwData )
{
	PWB35REG	pWb35Reg = &pHwData->Wb35Reg;

	if ((pWb35Reg->BB2C & BIT(11)) == 0)
		return 0;
	else
		return 1;
}
//----------------------------------------------------------------------------------------------------
VOID hal_set_antenna_number( IN phw_data_t pHwData, u8 number )
{

	PWB35REG	pWb35Reg = &pHwData->Wb35Reg;

    if (number == 1)
    {
        pWb35Reg->BB2C |= BIT(11);
    }
    else
    {
        pWb35Reg->BB2C &= ~BIT(11);
    }
	Wb35Reg_Write( pHwData, 0x102c, pWb35Reg->BB2C );
	#ifdef _PE_STATE_DUMP_
	WBDEBUG(("Current antenna number : %d\n", number));
	#endif
}
//----------------------------------------------------------------------------------------------------
ULONG hal_get_bss_pk_cnt( IN phw_data_t pHwData )
{
	PWB35REG	pWb35Reg = &pHwData->Wb35Reg;
	ULONG		val;

	if( pHwData->SurpriseRemove ) return 0;

	val = pWb35Reg->BB50;
	val &= 0xffffff1f;
	val |= 0x0000003f;	//BSS_PK_CNT
	pWb35Reg->BB50 = val;
	Wb35Reg_Write( pHwData, 0x1050, pWb35Reg->BB50 );

	Wb35Reg_Read( pHwData, 0x1060, &pWb35Reg->BB60 );
	return (pWb35Reg->BB60);
}
//----------------------------------------------------------------------------------------------------
//0 : radio on; 1: radio off
UCHAR hal_get_hw_radio_off( IN phw_data_t pHwData )
{
	PWB35REG	pWb35Reg = &pHwData->Wb35Reg;

	if( pHwData->SurpriseRemove ) return 1;

	//read the bit16 of register U1B0
	Wb35Reg_Read( pHwData, 0x3b0, &pWb35Reg->U1B0 );
	if ((pWb35Reg->U1B0 & 0x00010000))
	{
		pHwData->CurrentRadioHw = 1;
		return 1;
	}
	else
	{
		pHwData->CurrentRadioHw = 0;
		return 0;
	}
}
//----------------------------------------------------------------------------------------------------
BOOL hal_get_dxx_reg( IN phw_data_t pHwData, IN USHORT number, OUT PULONG pValue )
{
//	PADAPTER Adapter = pHwData->Adapter;
//	PWB35REG pWb35Reg = &pHwData->Wb35Reg;
	BOOL	ret;

	if( number < 0x1000 )
		number += 0x1000;
	ret = Wb35Reg_ReadSync( pHwData, number, pValue );
	return ret;
}
//----------------------------------------------------------------------------------------------------
BOOL hal_set_dxx_reg( IN phw_data_t pHwData, IN USHORT number, IN ULONG value )
{
//	PADAPTER Adapter = pHwData->Adapter;
//	PWB35REG pWb35Reg = &pHwData->Wb35Reg;
	BOOL	ret;

	if( number < 0x1000 )
		number += 0x1000;
	ret = Wb35Reg_WriteSync( pHwData, number, value );
	return ret;
}
//----------------------------------------------------------------------------------------------------
VOID hal_scan_status_indicate( IN phw_data_t pHwData, IN BOOLEAN IsOnProgress )
{
	if( pHwData->SurpriseRemove ) return;
	pHwData->LED_Scanning = IsOnProgress ? 1 : 0;
}
//----------------------------------------------------------------------------------------------------
VOID hal_system_power_change(  IN phw_data_t pHwData, ULONG PowerState )
{
	if( PowerState != 0 )
	{
		pHwData->SurpriseRemove = 1;
		if( pHwData->WbUsb.IsUsb20 )
			hal_stop( pHwData );
	}
	else
	{
		if( !pHwData->WbUsb.IsUsb20 )
			hal_stop( pHwData );
	}
}
//----------------------------------------------------------------------------------------------------
VOID hal_surprise_remove( IN phw_data_t pHwData )
{
	PADAPTER Adapter = pHwData->Adapter;
	if( OS_ATOMIC_INC( Adapter, &pHwData->SurpriseRemoveCount ) == 1 )
	{
		#ifdef _PE_STATE_DUMP_
		WBDEBUG(("Calling hal_surprise_remove\n"));
		#endif
		OS_STOP( Adapter );
	}
}
//----------------------------------------------------------------------------------------------------
VOID hal_rate_change( IN phw_data_t pHwData ) // Notify the HAL rate is changing 20060613.1
{
	PADAPTER	Adapter = pHwData->Adapter;
	UCHAR		rate = CURRENT_TX_RATE;

	BBProcessor_RateChanging( pHwData, rate );
//	RF_RateChanging( pHwData, rate );
}
//----------------------------------------------------------------------------------------------------
VOID hal_set_rf_power( IN phw_data_t pHwData, IN UCHAR PowerIndex )
{
	PADAPTER	Adapter = pHwData->Adapter;

	if( TS_RUNNING_IN_TESTSTA_MODE )
		return; // Ignore setting if access right is not owned by NDIS

	RFSynthesizer_SetPowerIndex( pHwData, PowerIndex );
}
//----------------------------------------------------------------------------------------------------
BOOL hal_set_LED( IN phw_data_t pHwData, IN ULONG Mode ) // 20061108 for WPS led control
{
	pHwData->LED_Blinking = 0;
	pHwData->LED_control = Mode;
	OS_TIMER_SET( &pHwData->LEDTimer, 10 ); // 20060623
	return TRUE;
}

